The development and integration of low-k materials for sidewall spacers has proven challenging, primarily due to their weakness, particularly resulting from downstream processing, e.g., etching, ashing, and/or cleaning. Conventional practices include the use of a robust film such as oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), etc. as a crust layer to protect the weaker low-k materials during the downstream processes. Such techniques are effective to reduce lateral erosion of the low-k materials, but provide minimal protection to spacer shoulder loss. These conventional approaches also result in unwanted epitaxial (EPI) growth, trench silicide-gate (TS-PC) short, and gate height variations. Further, such approaches prevent implementation of materials with lower dielectric constant (k) values to further boost device performance.
A need therefore exists for methodology enabling formation of a robust low-k sidewall spacer for downstream processes and the resulting device.